Nearest-neighbour parity gates without the determinant constraint are efficiently universal

There exists a positive natural number $C$ such that, for every effective source family $F$ having positive width $n_s$ at every finite Boolean string $s$, there is a family of ordered gate lists $G_s$ on $4n_s$ wires with the following properties. A source gate is either an arbitrary one-qubit unitary on a specified wire or controlled-$Z$ on specified wires $i,j$ satisfying $i+1=j$. To specify effectiveness, let $u(r)$ be the string of $r$ true bits and let $\tau([v_1,\ldots,v_\ell])$ concatenate $u(|v_j|)$, one false bit, and $v_j$ for each $j$. The source family’s code is $\tau([u(n_s),u(L_s)]\mathbin{+\!\!+}\text{gate descriptions})$, using $\tau([[{\rm false}],u(i)])$ for a one-qubit gate and $\tau([[{\rm true}],u(i),u(j)])$ for controlled-$Z$; this code must be polynomial-time computable from $s$. Its numerical list consists of the entries $(00,01,10,11)$ of each one-qubit matrix in gate order. There must also be a polynomial-time function which, on $\tau([s,u(j),u(r),[b]])$, approximates the real part of numerical entry $j$ if $b$ is false and its imaginary part if $b$ is true, to absolute error at most $2^{-r}$, for every valid $j$ and every natural precision $r$; its output is interpreted as a signed binary integer divided by $2^r$, with a true first bit indicating a negative sign and the tail encoding the magnitude, with missing bits read as false. Each target gate consists of two $2\times2$ unitary matrices $A,B$ and an injection selecting two distinct wires. Its local entry from $y$ to $x$ is zero if their two-bit parities differ, is $A_{x_0,y_0}$ when both parities are even, and is $B_{x_0,y_0}$ when both are odd. The target family has polynomial-time computable code $\tau([u(4n_s),u(|G_s|)]\mathbin{+\!\!+}[\tau([u(i_g),u(j_g)])]_g)$ and polynomial-time approximable numerical data consisting of the four entries of $A_g$ followed by the four entries of $B_g$ in gate order, with the same approximation convention. For every $s$, the two wires of each target gate have index difference at most $1$, and $|G_s|\le C L_s$. For every $s$, source wire $k$ of index $0$, target wire $q$ of index $0$, unit vector $\psi$ on length-$n_s$ bit strings, and Boolean $b$,

where $V_s,W_s$ apply their respective gate lists in listed order, with identity action on untouched wires. The quantifiers include the empty parameter string and empty source lists; an empty source list forces an empty target list through the length bound. The equality is required for the index-zero wires and every normalized input vector.