Pair encoding yields a range-three simulation

There exists a positive natural number $C$ such that every effective source family $F$ with positive width $n_s$ for every finite Boolean string $s$ admits a family of ordered gate lists $G_s$ on $2n_s$ wires satisfying the following conditions. Source gates are arbitrary one-qubit unitaries on specified wires or controlled-$Z$ gates on specified wires $i,j$ satisfying $i+1=j$. Here effectiveness uses the following encoding: $u(r)$ is $r$ true bits, and $\tau([v_1,\ldots,v_\ell])$ concatenates $u(|v_j|)$, a false bit, and $v_j$ for each $j$. The source code $\tau([u(n_s),u(L_s)]\mathbin{+\!\!+}\text{gate descriptions})$ must be polynomial-time computable, where a one-qubit description is $\tau([[{\rm false}],u(i)])$ and a controlled-$Z$ description is $\tau([[{\rm true}],u(i),u(j)])$. The numerical list records each one-qubit matrix’s entries in order $(00,01,10,11)$ and no entries for controlled-$Z$; a polynomial-time function on $\tau([s,u(j),u(r),[b]])$ must approximate the real part of data entry $j$ for false $b$ and its imaginary part for true $b$, within $2^{-r}$ for every valid $j$ and every $r\in\mathbb N$. Its output represents a signed binary integer divided by $2^r$, with a true initial bit denoting a negative sign and the tail giving the binary magnitude, with missing bits read as false. Each gate of $G_s$ specifies distinct target wires and two $2\times2$ unitary matrices $A,B$; the local matrix entry from $y$ to $x$ is zero between different parities, is $A_{x_0,y_0}$ on even parity, and is $B_{x_0,y_0}$ on odd parity. Every target gate satisfies $\det A=\det B$, its two wire indices differ by at most $3$, and $|G_s|\le C L_s$. The target code $\tau([u(2n_s),u(|G_s|)]\mathbin{+\!\!+}[\tau([u(i_g),u(j_g)])]_g)$ is polynomial-time computable, and its numerical list, comprising the four entries of each $A_g$ followed by the four entries of $B_g$, has a polynomial-time approximation procedure with the same convention. For every $s$, source wire $k$ with index $0$, target wire $q$ with index $0$, unit vector $\psi$ on length-$n_s$ bit strings, and Boolean $b$,

The operators $V_s,W_s$ apply their gate lists in listed order, each gate acting identically on untouched wires. Empty parameter strings and empty source gate lists are included; the length bound forces the target list to be empty when the source list is empty.